Ahmad Afifi

  Defense Session of PhD Thesis

  Abstract

  During the past several decades, the semiconductor industry has integrated more than two billion transistors on a single chip. However, this industry no longer relies on only transistor scaling for higher computing performance. It has been projected that in 2016 most CMOS circuits will be manufactured with 22 nm process. The CMOS circuits will have a large number of defects and can provide for the continuation of the

Moore's Law only for the next few years . Especially when the transistor goes below sub-micron, the original deterministic circuits will start having probabilistic characteristics. Hence, it would be challenging to map traditional Von-Neuman computational models onto probabilistic circuits, suggesting a need for fault-tolerant computational algorithms. Biologically inspired algorithms, or spiking neural networks (SNNs), exhibit a remarkable match to the nano-scale electronics, besides having great fault-tolerance ability. Research on the potential mapping of the SNNs onto a recently developed technology called hybrid CMOS/Nano circuits (such as CMOL) provides useful insight into the development of neuromorphic architectures that has a significant impact on the Intelligent Signal Processing (ISP) and the future of the nano-computer industry. In CMOL two-terminal nanodevices are arranged into a single layer as an add-on to a CMOS sub-system.

  In this thesis, we investigated asynchronous implementations of adaptive SNNs on different CMOS/Nano platforms, including molecular and memristive based crossbars. We provide spike-timing dependent plasticity (STDP) rule by modifying Integrate-and-Fire (I&F) type neurons in a biologically inspired and plausible approach. We show that the STDP rule can be provided using a crossbar array combined with neurons that asynchronously generate spikes of a given shape, similar to biological action potentials, and send them to both forward and backward directions along their axon and dendrites, simultaneously. The method eliminates storage circuits per synapse and so it can be mapped to crossbar-based CMOS/Nano hybrids rather easily. The obtained STDP learning function is exactly that of the STDP learning function obtained from neurophysiological experiments on real synapses.

  In this thesis, we draw the conclusion that the STDP rule in memristive based (analog) crossbars exhibit better performance in comparison to molecular (binary) crossbars. We also highlighted a number of options for cost-effective computational resources and power consumption. The simulated results show that the size and complexity of the proposed architecture have been improved in order of {O(N²)-O(N)} (where N is the network size) in comparison to regular CMOS based adaptive SNNs implementations.

  Furthermore, the performance of the rule as spike-timing correlation learning of synchrony detection and character recognition in winner-take-all (WTA) networks are demonstrated as case examples.

  Place: Seminar Room of Electrical Faculty