Seyyed Javad Seyyed Mahdavi Chabok

AWT IMAGE

Electrical Engineering Department

  Ph.D. Thesis Defense Session

396

  AWT IMAGE

  Evolutionary Design of Digital Reliable Circuits

  Abstract

  Reliability is currently a new factor in designing integrated circuits. In order to design a reliable circuit, effective methods for reliability analysis apart from its manufacturing technology are required. Due to recent developments in manufacturing of reconfigurable hardware, the evolutionary approach for designing circuits is of interest .

  This thesis considers reliability improvement of digital circuits by evolutionary approach. An appropriate environment is proposed for evolutionary design of combinational and sequential circuits which has features such as proper chromosome structure for applying evolutionary operators, using general VHDL file for nonstop circuit simulation and possibility of slicing the initial set of elements to reduce GA’s search space. T o attain thesis aims, methods for reliability analysis of combinational and sequential digital circuits are presented.

  Results show that improved single-pass method is fast and dependable for reliability analysis of combinational circuits and it can reduce maximum error from 50% to 7% in a circuit with large number of re-convergent fan-outs such as C1355 with gate failure rate of 0.1. Multiple-pass method also has mean absolute error near 5 percent in all nodes reliability analysis of a sequential circuit with 150 gates and 4 D-flip-flops.

  In addition to improving circuit’s reliability, the proposed method is also capable of optimizing other parameters such as power consumption, speed and silicon area with less priority to reliability. By applying proposed method to a set of benchmark circuits, it is shown that more reliable circuits (about 20 percent improvement) can be generated by this method in comparison to primary circuits. Moreover, the scalability issue limits this method to be applied only to basic digital circuits such as multiplexers, decoders and flip-flops.

  Candidate: Seyyed Javad Seyyed Mahdavi Chabok

  Supervisor: Dr. K. Mohammadi

  Examining Committee :

  Dr. H. Taheri, Dr. A. Khademzadeh, Dr. S. Baradaran Shokouhi,

  Dr. S. Shah Hoseini, Dr. S. Mirza Kuchaki

  Date: Wed, 2010-09-15 16:30

  Place: Conference room of Electrical Engineering Dep.

 


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