1- Faculty profile | Family Name: Naderi | First Name: Majid | • Title: Associate Professor | Contact imformation: | Tel: 021-77491237 ,09123874128 Fax: 021-77491237 URL: http://crypto.iust.ac.ir | Email : m_naderi(At)iust.ac.ir | 2- Higher Education • B.S.c. 1966, Electrical Engineering, Electrical & Electronic Engineering Dept., Iran University of Science & Tech., Distinction : First Rank, Honors.
• M.S.c. 1974, Application of Digital Technique in Control and Communication; Electrical & Electronic Eng. Department, Herriot - Watt University, Edinburgh EH1 2HT Scotland, U.K.
• Ph.D. 1977, Electronic Engineering, The Electronic Laboratories; University of Kent, Canterbury; Kent CT2 7NT England, U.K. | 3- Expertise 1. Parallel Processing
2. Computers Architecture
3. Microprocessors Base Design
4. ATM Switches
5. Automation
6. Design of Digital Systems
7. Cryptography & Secure Systems
8. Advance Computers Architecture | 4- Taught Couses 1. Parallel Processing
2. Advance Computer Architecture
3. Computer Organization
4. Microprocessors based design
5. Microprocessors
6. Computer Interfacing
7. Logic Design Principle
8. Advance Logic Design | 5- Research and Industrial Projects: 1. Design and Development of the "DLTS" system for test and measurement of the semiconductor devices, 1992 2. Design and Development of the "Data Acquisition and Monitoring of Powerplant", 1990 3. Modeling and Performance Evaluation of Multiprocessors system, 1991. 4. Design and Development of the "Remote Telemetry Unit", 1988. 5. Design and Implementation of "Arbiter Switches", 1984. 6. Design and developed of the "VINS" for position determination, 1990. 7. Design and developed of the "Automatic Weather Observation System", 1988. 8. Design and developed of "Remote Automatic Weather Observation System" (RAWOS), 1991. 9. Design and developed of "Remote Automatic Industrial Sequencer", 1990. 10. Design and developed of "Industrial Information Center", 1990. | 6- Journal Papers : [1]. M.Naderi,” Modelling and Performance Evaluation of Multiprocessors Organisation with shared Memories” ; ACM Computer Architecture News Vol. 16 , No. 4 , sept. 1988 , pp.51-74 .
[2]. M.Naderi, “Modelling and Performance Evaluation of Multiprocessors Organization with Multi-Memory Units”;ACM Computer Architecture News, Vol.16 , No.5 , Dec.1988,pp.35-51.
[3]. M.Naderi; “A Micro Computer based design for the Data Acquisition and Monitoring of Power plant” ; System Science Journal , Vol.17, No.3 , 1991 .
[4]. G.S. Markarian, M. Naderi, B. Honary, A. Poppiwell and j.j. O`Reilly ;” Maximum likelihood decoding of RLL/FEC array codes on partial response channels”, Electronics Letters ,5th August 1993, Vol.29, No.16, pp.1406-1408 .
[5]. A. Naseri, H. S. Shahhoseini, M. Naderi. "Clustering Of Interleaved Pulses Using Systolic Array", IUST-International Jornal of Engineering Science, Vol.15, No.3, pp. 101-107, 2004
[6]. A.Mohsseni , M.Naderi, "IUSTA, A Prioritized Multicast ATM Switch: Design & Performance Evaluation," Iranian Journal of Science & Technology, Vol. B4-27, pp.771-782, 2003.
[7]. H. S. Shahhoseini; M. Naderi ;” Reaching to the Best Performance on the Superscalar Processors", ACM Computer Architecture News, Vol. 27, No.4, pp 6-11, Sep 1999.
[8]. K.Hassanli, A. K. Mahani,M. Naderi,”The Impact of Hidden Terminal on WM Net Performance”, Springer –Verlag, Berlin Hiedelberg,2008.
[9]. A. K. Mahani, H. F. Rashvand, M. Naderi, B.Abolhasani,”Wireless Mesh Networks Channle Reservation: Modelling And Delay Analysis”, IET Communication, 2008.
[10]. A. K. Mahani, M. Naderi, C.Casetti,C.F. Chiasserini,”Enhancing Channel Utilization Mesh Networks”, International Journal of Electronics and Communications,AEU,2008.
[11]. A. K. Mahani, M. Naderi, C.Casetti,C.F. Chiasserini,”Mac-Layer Channle Utilisation Enhancements For Wireless Mesh Networks,” The Institution of Engineering and Technology(IET),2009.
[12]. Y.S.Kavian,W.Ren, M.Naderi, M.S.Leeson and E.L.Hines,”Fault Tolerant Dense Wavelength Division Multiplexing Optical Transport Networks”,Journal of Telecommunications and Information Technology,pp.63-67,2009.
[13]. Y.S.Kavian,H.F.Rashvand,M.S.Leeson,W.Ren,E.L.Hines and M.Naderi,”Network Topology Effect on Qos Delivering in Survivable DWDM Optical Networks”,Journal of Telecommunications and Information Technology,pp.68-71,2009.
[14]. Y.S.Kavian,H.F.Rashvand,M.S.Leeson,W.Ren,E.L.Hines and M.Naderi,”Generic Algorithm Optimization for DWDM Network Capacity Planning Under Loading Uncertainty,” IEEE Communications Letters –pp.1-3,2009. | 7- Confrence papers: [1]. M.Naderi; “Modelling and Performance Evaluation of Multi processors organization with Multi - Memory units” , International Conferance on Systems Science , Wroclaw , Poland ; 19-22 Sept . 1989 .
[2]. M.Naderi; “A Micro- computers Based Design for Data Acquisition and Monitoring of Power Plant” ; International Conferance on Systems Science , Wroclaw , Poland ; 19-22 Sept. 1989 .
[3]. M.Naderi; “Modelling and Performance Evaluation of Real Time Computer Organization” ; Proceeding of the 7th International Conferance on System Engineering ; july 18-20 , 1990 , Las Veggas , USA .
[4]. M.Naderi;” Modelling & Performance Evaluation of Real – TimeComputer Organization” , International Conferance on Control and Modelling - ICCM’90 , july 17- 20 1990 , Tehran , Iran pp.513-516 .
[5]. G.S. Markarian , B. Honary, M. Naderi;” RLL/FEC Design Based on Generalised Array codes”, International Symposium On Communication Theory & Application , 11 – 16 july , 1993 Lake District , England ; U.K.
[6]. M. Naderi, B. Honary , G.S. Markarian ; “Low complexity soft maximum likelihood decoding of RLL/FEC codes” .proceedings of IEE international conferance on Telecommunications, 19-21 january 1994. Dubal , UAE .
[7]. M.Naderi; “Modellings Concepts and Networks Analysis tools for futur IBC Networks” ; Proceedings of 1990 Biikent International Conferance on New Trends in Communication, Control and Signal Processing, Biikent University , Ankara Turkey , 2-5 july , 1990 , pp. 24-30
[8]. M. Naderi;” Queuing Models and Simuiation Studies of Access Conflicts in Multi –Micro – Processors Networks”, Proceedings of International Conferance on Applied Mathematics, june 18-20 , 1991 – Tehran , Iran
[9]. M.Naderi; “Evaluation of Performance Communication in Multiprocessors Organization Networks”; Proceedings of UK-USSR International Symposium on Communication Theory and Applications , Crieff , Scotland , 9-13 Sept-1991.
[10]. M.Naderi; G.S.Markarian; B. Honary; j.j.O’Rilly and A. Poppiewell,” Trellis Decoding of RLL codes with Error Protection”,IEE – 5th Bangor Communication Symposium , 2-3 june 1993 , University of Waies Bangor , U.K.
[11]. M.Naderi,”An Improved Model For Performance Evaluation Of Multiple Bus Multiprocessor System”,IASTED,30march-2 April ,1998.
[12]. M.Naderi, ”Performance Evaluation And Cost Analysis Of A Parallel Processing System With Shared Memory”, Proceeding Of Applied Modeling And Simulation, 12-14 August,1998.
[13]. Y. S. Kavian, A. Falahati, A. Khayatzadeh, M. Naderi, "High Speed Reed-Solomon Decoder with Pipeline Architecture", Second IEEE and IFIP International Conference on wireless and Optical Communications Networks, WOCN 2005, Page(s):415-419, March 6 - 8, 2005.
[14]. H.M.Naimi,M.Naderi,H.S.SHahhosseini,”Virtual Service Center: A Closed Form Model For Crossbar-Based Multiprocessors”,Proceeding of th IASTED International Conference Applied Simulation And Modeling,June 25-28, 2002,Crete, Greece,92-96.
[15]. H.M.Naimi,M.Naderi,H.S.SHahhosseini,”Uniformly Distributed Sampling: An Exact Algorithm for GA’s Intial Population In a Tree Graph”, Proceeding of th IASTED International Conference Applied modeling, Simulation And optimization, June 2-4. Banff, Alberta,Canada, 2003.
[16]. H.M.Naimi,M.Naderi “Uniformly Distributed Sampling: An Exact Algorithm for GA's Initial Population In a TREE Graph”, Proceeding of the International conference on Modeling, Simulation and Optimization (MSO 2003), Banff, Canada, July 2003.
[17]. A. Khayatzadeh Mahani, H.S. Shahhoseini, M. Naderi, "Fixing Scale Factor In Systolic Cordic Dct", ISCTA2003, July 2003, U.K.
[18]. A Mohsseni , M.Naderi,"Distributed Output Port Controller And Multiplexer For Iusta Atm Switch" Proceeding of the First Northeast Workshop on Circuits and Systems NEWCAS 2003.
[19]. A. Naseri, H. S. Shahhoseini, M. Naderi "Conical Systolic Array For Matrix Inversion", Proceeding of International Conference on Modeling & Simulation, Palm Springs, California, USA, Feb 2003.
[20]. A. Naseri, M. Naderi "Systolic processor for observability analysis in dispatching networks," Proceeding of Conference on Electrical Engineering, Ahvaz, Iran, Dec.2002, 245-252.
[21]. A. Naseri, H. S. Shahhoseini, M. Naderi "Data Clustering by Minimum Difference Tree and PRI Transform," Proceeding of Workshop on Recent Progress in Computers and Communication, EurAsia ICT 2002, Shiraz, Iran, pp. 35-39, Oct. 2002.
[22]. A. Naseri, H. S. Shahhoseini, M. Naderi "A New Matrix Method For Pulse Train Identification: Implementing by Systolic Array," XI° European Signal Processing Conference, Toulouse, France, pp.19-22, Sept. 2002.
[23]. A. Naseri, H. S. Shahhoseini, M. Naderi "Matrix Multistage Clustering of Interleaved Pulse Train," Proceeding of Signal Processing, Pattern Recognition and Applications, SPPRA2002, pp. 98-101 Crete, Greece, June 2002.
[24]. A. Naseri, H. S. Shahhoseini, M. Naderi"A New Matrix Method For Pulse Train Identification," Proceeding of 11TH IEEE MELECON conference, Cairo, EGYPT, PP.183-187, May 2002.
[25]. H. S. Shahhoseini; M. Naderi.; "Performance Analysis of IUSTA Priority Mechanism" Proceeding of the ConfTele2001, pp.25-30, Coimbra, Portugal, April 2001.
[26]. H. S. Shahhoseini, M. Naderi "Design Tradeoff on Shared Memory Clustered Massively Parallel Processing System," Proceeding of the 10th International Conference on Computing and Information, ICCI2000, Kuwait, Nov.2000.
[27]. Shahhoseini, H. S ; M. Naderi "Shared Memory Multistage Clustering Structure, An Efficient Structure for Massively Parallel Processing System," Proceeding of the 4th IEEE International Conference on High Performance Computing Proceeding, pp.22-27, Beijing, China, May 2000.
[28]. H. S. Shahhoseini, M. Naderi, "Upper Bounds in Modified Models of Speedup in Parallel Machines," Proceeding of 17th International Conference on Applied Informatics, Innsbruck, Austria, pp.239-243, Feb 2000.
[29]. M.Safkhani ،N.Bagheri, M.Naderi, “Cryptanlysis of the L-pipe Hash Structure," ICEE 2009.
[30]. N.Bagheri, M.Naderi,” Web Based Education”, 1st national conference in engineering development in Education, Iran, Tehran,2002,( in Persian).
[31]. A.Falahati, N. Bagheri, M. Naderi, J. Mohajeri, “A new distinguish attack against ABC stream cipher”, The 9th international conference on Advanced Communication Technology, Korea, 2007.
[32]. N.Bagheri, M.Naderi,” New enhancement to MDx Hash Function class by linear error correction codes”, ISCC 2007.
[33]. N.Bagheri, M.Naderi, B.Sadeghiyan “Multi-collisions in Ring Hash Structure” SECRYPT 2008, Porto, Portugal.
[34]. N.Bagheri, M.Naderi, B. N.Bagheri, M.Naderi,” Web Based Education”, 1st national conference in engineering development in Education, Iran, Tehran,2002,( in Persian).
[35]. A.Falahati, N. Bagheri, M. Naderi, J. Mohajeri, “A new distinguish attack against ABC stream cipher”, The 9th international conference on Advanced Communication Technology, Korea, 2007.
[36]. N.Bagheri, M.Naderi,” New enhancement to MDx Hash Function class by linear error correction codes”, ISCC 2007.
[37]. N.Bagheri, M.Naderi, B.Sadeghiyan “Multi-collisions in Ring Hash Structure” SECRYPT 2008, Porto, Portugal.
[38]. Sadeghiyan, M.Safkhani “Cryptanlysis of L-Pipe Hash Structure” 17th ICEE 2009, Tehran, Iran.
[39]. N.Bagheri, M.Naderi, B.Sadeghiyan “A Model for Designing Compression”17th ICEE 2009, Tehran, Iran (In Pesian).
[40]. N.Bagheri, M.Naderi, B.Sadeghiyan “Multi-collisions in Zipper-Hash Structure” Tenth International Symposium on Communication Theory and Applications (ISCTA) 2009, Ambleside, Lake District, UK.
[41]. B.Kasiri,H.Meshgi M.Naderi and B.Abolhassani,”Diversity Based Relay Selection for Multihop Cellular Networks”,International Conference on Advanced Computer Theory and Engineering,2008.
[42]. B.Kasiri, M.Naderi and B.Abolhassani,”A New Realistic Relay Selection Method Based on Correlated Shadowing for Multihop Cellular Networks”,International Conference on Computer and Electical Engineering,2008.
[43]. H.Meshgi,B.Kasiri, M.Naderi and B.Abolhassani,” On the Performance of A New Relay Selection Scheme in Multihop Cellular Networks”,International Conference on Computer and Electical Engineering,2008. | 8- Books: 1 . Advance Computer Architecture and Parallel Processing; M. Naderi
Iran University of Science & Technology; 1998 .
2 . POWER And POWER PC ;Principal , Architecture and Implementation
Translated by : M. Naderi and H.M. Naimi; 2003
Iran University of Science & Technology.
3 . Computer Architecture ,Translated by : M. Naderi and S. Razei ; 2003 , Naghos Co.
4 . Hash Function : Cryptography and Secure System ; 2006 ,
Iran University of Science & Technology ; M. Naderi , M.Safkhani ,
5 . Pulse Technique , M. Naderi
Amirkabir University Press ; 1988 | 9- Professional Activities 1-Institute of Electrical Engineers (IEEE)
2-Iranian Society of Control & Instrumentation Engineers
3-MRS Society
4-International Federation For Information Processing (IFIP)
5-IFIP - WG 6.6 (Network Management for Communication Networks)
6-IFIP – TC6 Information Network and Data Communication ,II | 10- Technical Report : Administrative Responsibilities: • 2001–2009, Head of The Secure Communications, School of Electrical Engineering; Iran University of Science & Technology.
• 1993-2001, Associate Professor Department of Electrical and Electronic , Iran University of Science & Technology .
• 1991-1993, Visiting Professor of Engineering Department, Lancaster University, Lancaster LA1 4YR, England, U.K.
• 1986-1991, Associate Professor, Department of Electrical & Computer Engineering, Iran University of Science & Technology
• 1985-1988, Head of Computer Center, Iran University of Science & Technology.
• 1982-1985, Head of Computer Department, Iran Univ. of Science & Technology.
• 1978-1981, Head of the Electrical and Electronic Department of Engineering.
• 1977-1986, Assistant Professor, Electrical & Electronic Engineering Department, Iran University of Science & Technology.
• 1970-1977, Instructor, Electrical & Electronic Engineering Department, Iran University of Science & Technology. | 11- Postgraduate Projects: PHD Projects:
1.Design An Expandable Multicast ATMS Switch By Alireza Hesam Mohseni
2. Structural Design and Modeling of the Multistage Clustering Parallel Processing System. By Hadi Shahriar Shah Hoseini
3. Design, Modeling And Optimization Of Survivable DWDM Optical Transport Mesh Networks. By Youesf Seifi Kavian
4.MAC Layer Modeling & Fuzzy Based Priority Scheduling In Wireless Ad Hoc Networks By Ali Khayat Zade Mahani
5- Design and Cryptanalysis of Cryptographic Hash Functions. By Nasour Bagheri
Master Of Science Projects:
1. Deep Level Transient Spectroscopy. By Ali Sadr
2. Attitude And Heading Reference System. By Mohammad Reza Salehi
3. Mathematical Modeling Of Multi Processors System. By Kave Fazli
4. Design, Simulation & Synthesis Of New Co Processor For Computing 2D-DCT/IDCT By Ali. Khayatzade Mahani
5.Real Time Digitizing Of Video Images And Divided Them For Sending to A Narrow Band Channel. By Bita Naseri
6.A Key Management Architecture For Securing Off –Chip Data Transfers On An FPGA. By Sofia Ahanj
7.Design And Simulation Of Networks Interface Board For Cryptographic And Security In Ethernet LANs. By Maryam Dabardani
8.The Optimization Of VGAP Protocol Base On Qos In Ad-Hoc Networks. By Khadijeh Ghaferin
9.Integrated Circuit Design Of The Output Port Of An Industrial Automation System Using CMOS Technology. By J. Gholami Ahangarani
10. Buffer Overflow Vulnerability Assessment And Methods To Prevent Them. By Nazli Ahmad Khan Beigi
11. Quantum Cryptography Simulation With Quantum Key Distribution. By Hossein Shafie
12. Fault Attacks Analysis On Stream Ciphers. By Saharsadat Farnoodi
13. Multi Purpose Hash Algorithm Design. By Zahra Heydaran Daroogheh
14. Resource Allocation Enhancement In Multi Hop Cellular Networks. By Behzad Kasiri
15. Designing A Crypto Processor For Block Ciphers . By Mojde Mahajerani
16. Design And Simulation Of 32 Bit Crypto Processor For Cryptographic Applications. By Abouzar Ehsani Banafti
17.Adaption And Improvement Of The TCP Protocol Operation In Ad-Hoc Networks. By Seyed Roohollah Mirakbari
18. Documents Protection By Cryptographic Hash Function. By Masoumeh Safkhani
19. Design & Simulation Of Pipe Line Unit Of a Processor. By Ali Maknoni Nejad
20. Security In LANs. By Leili Esmasilani
21. Quantum Cryptography Simulation with Quantum Key Distribution. By Hosein Shafiei
B.S.c Projects:
1.Portable Automatic Weather Observation Station: By Alireza Nejat Pour-Said Mahvis
2.Text Editors: By Maziar Shojaei
3. Design And Manufacture Of EEPROM. By Mojgan Nazari
| 12- Honors, Recognition and Outstanding Achievements for Teaching and Research:
| 13- Research Labs: Cryptography and secure systems lab 
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