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phoeniX: A RISC-V Platform for Approximate Computing Version 0.1 Technical Specifications |
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| | Post date: 2023/11/27 | |
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phoeniX: A RISC-V Platform for Approximate Computing Version 0.1 Technical Specifications
Arvin Delavari
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran |
Faraz Ghoreishy
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran |
Hadi Shahriar Shahhoseini
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran |
Sattar Mirzakuchaki
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran |
PDF │ Abstract │ Keywords │ References │ Cite This
Abstract:
The phoeniX RISC-V processor project was initiated in the summer of 2023 at the Electronics Research Center of Iran University of Science and Technology. Led by two academic research laboratories, Super Computing and Networking (SCaN) Research Lab and the Circuit Design Research Lab, the primary objective of this project is to design a foundational processor for architectural research and development especially for the emerging field and concept of approximate computing. While numerous open-source processors have been developed by universities, organizations and individuals on GitHub, many of them possess complex design and simulation processes that hold computer architecture researchers from finding a suitable foundation for their research endeavors.
Many of these cores do not meet the needs and have a huge lack of flexibility, in order to be changed and in the following case, supporting fundamentals and special features of approximate computing. The ultimate goal of this project is removing these complexities for developers and enthusiasts of different branches in computer architecture. In fact, phoeniX is a novel embedded hardware platform for integration of approximate arithmetic units with a RISC-V processor, designed for developers in order to implement and test their approximate units in a unified processor using standard compilers such as GCC, with minimum changes and effort, by following simple guidelines for setup and simulations.
This document maintains technical specifications for the version 0.1 of the project which is a base RV32I processor, in order to be a platform and foundation for upcoming updates and features related to approximate computing.
Keywords: RISC-V; Approximate Computing; Embedded Systems; Modular Design; Open-Source Processors
References:
[1] “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213”, Editors Andrew Waterman and Krste Asanovic, RISC-V Foundation, December 2019.
[2] Yosys Open-Source Projects: https://www.yosyshq.com/open-source.
[3] Vesta Static Timing Analysis: http://www.maaldaar.com/index.php/vlsi-cad-design-flow/vesta
[4] C. Wolf. Yosyshq/picorv32: Picorv32 - a size-optimized risc-v cpu. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/YosysHQ/picorv32
[5] lowRISC lowRISC/ibex: Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/lowRISC/ibex
[6] riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/riscv-collab/riscv-gnu-toolchain
[7] Stephen Williams steveicarus/iverilog: Icarus Verilog. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/steveicarus/iverilog
[8] AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertions User Guide: https://developer.arm.com/documentation/dui0534/b/?lang=en
[9] riscv-software-src/riscv-tools: RISC-V Tools (ISA Simulator and Tests). Last Accessed: September 19, 2023. [Online]. Available: https://github.com/riscv-software-src/riscv-tools
[10] Qflow 1.3: An Open-Source Digital Synthesis Flow : http://opencircuitdesign.com/qflow/
[11] Oklahoma State University System on Chip (SoC) Design Flows: https://vlsiarch.ecen.okstate.edu/flow/
[12] efabless/raven-picorv32: Silicon-validated SoC implementation of the PicoSoc/PicoRV32. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/efabless/raven-picorv32
[13] Magic VLSI Layout tool: http://opencircuitdesign.com/magic/
[14] Netgen version 1.5 netlist comparison (LVS) and format manipulation: http://opencircuitdesign.com/netgen/index.html
[15] Odin II, logic synthesis and elaboration tool: https://docs.verilogtorouting.org/en/latest/odin/67
[16] berkeley-abc/abc: ABC: System for Sequential Logic Synthesis and Formal Verification. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/berkeley-abc/abc
[17] rubund/graywolf: graywolf is used for placement in VLSI design. Last Accessed: September 19, 2023. [Online]. Available: https://github.com/rubund/graywolf
[18] Qrouter version 1.3 (stable) and 1.4 (development) multi-level, over-the-cell maze router: http://opencircuitdesign.com/qrouter/
Cite this paper as:
A. Delavari, F. Ghoreishy, H. S. Shahhoseini and S. Mirzakuchaki. (2023), “phoeniX: A RISC-V Platform for Approximate Computing V0.1 Technical Specifications,” [Online]. Available: http://ee.iust.ac.ir/page.php?slct_pg_id=20291&sid=45&slc_lang=en
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