phoeniX: A RISC-V Platform for Approximate Computing
Contributors: Arvin Delavari, Faraz Ghoreishy, H. S. Shahhosseini, S. Mirzakuchaki
The phoeniX project was initiated in the summer of 2023 at the Electronics Research Center of Iran University of Science and Technology. Led by two academic research laboratories, Super Computing and Networking (SCaN) Research Lab and the Circuit Design Research Lab. The primary objective of this project is to design a foundational processor for architectural research and development, especially in field of approximate computing.
While numerous open-source processors have been developed by universities and individuals on GitHub, many of them possess complex design and simulation processes that holds computer architecture researchers from finding a suitable platform for their research endeavors. One of our most important goals in this project was removing these complexities for developers and enthusiasts of this field, along with maintaining and increasing the quality of experiences.
The phoeniX 32-bit processor, has a modular and extensive design, which is highly beneficial for developers, as it facilitates testing and research on computer architecture techniques. A key aspect of this processor is the removal of the traditional and classic “Control Unit” found in most RISC processors. Instead, each module in the processor can generate its own control signals based on the fields of the instruction it receives after the decode stage. All submodules are equipped with self-controllability feature and this principle is called “Self-Control Logic”. This microarchitecture, helps us with the modularity and extensiveness of the top module which is the phoeniX core.
Figure 1. phoeniX processor block diagram
But how does this microarchitecture benefit digital design and computer architecture developers and make the phoeniX core different from other available open-source RISC-V processor? This processor is designed to be a global and high quality foundation for implementation of “Approximate Computing” techniques, on RISC-V processor.
Approximate computing is an emerging paradigm for energy-efficient and high-performance designs. It includes various sets of computation techniques that return a possibly inaccurate result rather than a guaranteed accurate result, and that can be used for applications where an approximation is sufficient for its purpose. One example of such situation is for a search engine where no exact answer may exist for a certain search query and hence, many answers may be acceptable. Similarly, occasional dropping of some frames in a video application can go undetected due to perceptual limitations of humans.
The key goal of this project is to design an embedded platform in a way that user can even integrate accuracy controllable approximate module to phoeniX execution engine. The flow is getting carefully crafted to provide users and developers with a wide range of possibilities utilizing the default execution units of the phoeniX platform, allowing them to incorporate their own custom-designed operators. Users will have the flexibility to choose between approximate and accurate arithmetic, with the ability to seamlessly switch between these modes within both the developer design and the demo design.
In our initial release, known as phoeniX Version 0.1, the processor supports the RV32I instruction set. Our work showcases a new platform for embedded approximate computing, which in version 0.1 the base RV32I processor is developed, and in future updates which are coming very soon, extensions for approximate computing will be added. Version 0.2 which will be covering RV32IM instruction set and new unique features to advance approximate computing for image processing and edge AI development, will be released very soon.
The code has been carefully crafted to enable the utilization of the processor as a synthesizable and implementable soft-core on Xilinx FPGA devices. While the core is entirely synthesizable, it is important to note that implementation is limited to Xilinx Ultrascale and Ultrascale+ series of AMD Xilinx FPGA devices, owing to the processor’s pipeline size requirements.
The physical design and layout of phoeniX was done using Qflow, a popular open-source VLSI (Very Large Scale Integration) design tool. Qflow is a complete design flow that encompasses various stages of the VLSI design process, including synthesis, placement, routing, and verification. The OSU018 technology, also known as the TSMC 0.18-micron process technology, which was used for phoeniX layout design, is a widely adopted semiconductor fabrication process developed by Oklahoma State University.
  Figure 2. phoeniX processor physical layout
In conclusion, the phoeniX project has successfully developed a modular and extensive processor design for architectural research and development, including a novel way of integrating approximate computing within an embedded RISC-V core, which was the key goal of this project. With its simplified execution process, elimination of complexities, and comprehensive documentation, the processor offers a user-friendly experience for both developers and researchers. Overall, the phoeniX processor project provides an excellent platform for developers and researchers in the field of RISC-V computer architecture and approximate computing and it encompasses all the essential benefits required for their work and designs.
phoeniX GitHub page: https://github.com/phoeniX-Digital-Design/phoeniX
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